Published in IEEE Transactions on Electron Devices, 2022
Recommended citation: A. K. Gundu and V. Kursun, "5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets," in IEEE Transactions on Electron Devices, vol. 69, no. 3, pp. 922-929, March 2022, doi: 10.1109/TED.2022.3143774.
Download Paper
Published in VLSI, The Integration, 2021
Recommended citation: G. Anil Kumar and V. Kursun, “Novel Low Leakage and Energy Efficient Dual-Pullup/Dual-Pulldown Repeater,” Integration, The VLSI Journal. Vol. 78, Pp. 110-117, February 2021.
Download Paper
Published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019
Recommended citation: A. Kumar Gundu and V. Kursun, "Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input–Output Repeaters," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 7, pp. 1537-1547, July 2019, doi: 10.1109/TVLSI.2019.2902215.
Download Paper
Published in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024
Recommended citation: A. K. Gundu, L. Fassio and M. Alioto, "E-Textile Battery-Less Walking Step Counting System with <23 pW Power, Dual-Function Harvesting from Breathing, and No High-Voltage CMOS Process," 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2024, pp. 1-2.
Download Paper
Published in IEEE International Symposium on Circuits and Systems (ISCAS), 2022
Recommended citation: A. K. Gundu and V. Kursun, "Impact of Sheet Width and Silicon Height in 3D Stacked Nanosheet GAA Transistor Technology," 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 2547-2550.
Download Paper
Published in IEEE 34th International System-on-Chip Conference (SOCC), 2021
Recommended citation: A. K. Gundu and V. Kursun, "Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology," 2021 IEEE 34th International System-on-Chip Conference (SOCC), Las Vegas, NV, USA, 2021, pp. 25-28.
Download Paper
Published in International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019
Recommended citation: A. K. Gundu and V. Kursun, "Energy Efficient Clock Distribution with Low-Leakage Multi-Vt Buffers," 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodes, Greece, 2019, pp. 113-118.
Download Paper